1. Field of the Invention
This invention relates to a method for correction of hold time errors for LSI logic circuits (integrated circuits) and a program for same, and in particular relates to a hold time error correction method and program which satisfies all of a plurality of timing constraints corresponding to a plurality of operating modes. Moreover, this invention provides a layout method and program which do not generate timing errors under a plurality of timing constraints. The hold time error is sometimes called as a hold time violation. In this specification, “hold time error” or “hold error” is commonly used as the hold time violation.
2. Description of the Related Art
As the logic circuitry within semiconductor integrated circuit chips has increased in scale and moved to higher speeds, it has become increasingly difficult to perform layout while checking signal timing. Conventional layout tools are programs which perform layout of logic circuits on a computer; based on the logic data of a logic circuit the logic design of which has been completed, the cells and macros comprising the logic circuit are arranged on the chip, and a post-layout netlist is generated. Layout tools normally incorporate static timing analysis (STA) tools, so that layout which takes signal timing into account can be performed.
The signal static timing includes the setup time, which indicates how far ahead of the clock the supplied data should be set up, and the hold time, which indicates how long after the clock the supplied data should be held. Both the setup time and the hold time constraints must be satisfied.
FIG. 1 is a figure explaining the above setup time and hold time. The flip-flop shown in FIG. 1A reads the supplied data DATA on the rising edge of the clock pulse CLK, and outputs the data from the output Q. In order to appropriately read the data DATA in response to the clock CLK, the data DATA must be finalized earlier than the timing of the clock CLK by at least the length of the setup time, and must be held until after the hold time.
FIG. 1B shows the setup time; the setup time ST is the time between the moment of finalization of the data DATA and the rising edge of the clock signal CLK, and is required to be at least the setup time determined by the flip-flop characteristic. FIG. 1C shows the hold time. The hold time is the time between the rising edge of the clock signal CLK and the end of the data DATA, and is also required to be at least the hold time determined by the flip-flop characteristic.
The earlier the finalization of the data DATA, the more easily the setup time ST requirement can be met. After layout of the logic circuit, however, it is difficult to advance the timing of the data DATA. On the other hand, the later the end of the data DATA, the more easily the hold time HT requirement can be met; but even after completion of the logic circuit layout, it is easily to delay this timing by inserting a delay buffer.
The circuit delay characteristics will differ depending on the LSI process conditions, power supply voltage, and operating temperature. For example, if the process conditions fluctuate toward poorer conditions (characteristics become slower), the power supply voltage fluctuates toward lower voltages, and the operating temperature fluctuates toward higher temperatures, then the circuit delay will increase, and operating speed will be slowed. This is called the MAX (or maximum) side delay characteristic. Conversely, if the process conditions fluctuate toward better conditions (characteristics become faster), the power supply voltage fluctuates toward higher voltages, and the operating temperature fluctuates toward lower temperatures, then the circuit delay is reduced, and the operating speed increases. This shall be called the MIN (or minimum) side delay characteristic.
In setup time analysis, if analysis is performed using the MAX side delay characteristic, a check can be performed to determine whether setup time errors (or violations) occur; but in hold time analyses, in addition to the MIN side delay characteristic, analysis using the MAX side delay characteristic is also necessary. This is because a reversal phenomenon may occur between the hold time for MAX-side delay characteristics and the hold time for MIN-side delay characteristics, along signal paths where cells dominate and signal paths where wiring dominates.
If the above setup time requirement is not satisfied, a setup time error or violation (hereafter simply “setup error”) occurs, and if the hold time requirement is not satisfied, a hold time error or violation (hereafter simply “hold error”) occurs. When performing layout of a large-scale integrated circuit, cells and macros must be arranged so as to satisfy these timing requirements.
Conventional layout tools incorporate a static timing analysis (STA) tool which analyzes the setup time and hold time, and determines whether setup errors or hold errors have occurred, so as to perform layout which takes these timing requirements into consideration.
On the other hand, in some cases the integrated circuit has a plurality of timing constraints corresponding to a plurality of operating modes. Timing constraints mean constraints in which, for example, in a given operating mode two types of clock CLK1, CLK2 (at respective frequencies F1, F2) are used as control clocks, and in another operating mode, one type of clock CLK1 and its inverted clock /CLK1 (at frequency F3) are used as control clocks. In other words, in some cases the types of clocks used differ depending on the operating mode, and moreover the clock frequencies differ as well. Hence in integrated circuit layout, it is necessary that the above timing requirements be satisfied given a plurality of timing constraints corresponding to this plurality of operating modes.
As explained above, conventional layout tools incorporate a static timing analysis (STA) tool to perform layout, taking into account signal timing for one type of timing constraint (operating mode). It is difficult to modify the layout to advance the timing after the layout is completed. Hence in layout tools, layout of cells is performed such that setup errors do not occur, and then, after layout, the integrated circuit is checked for hold errors, and delay buffers are inserted into signal paths causing hold errors to correct the hold errors.
However, this hold error correction has the following problems. First, if a delay buffer is inserted in order to correct a hold error, a hold error for one type of timing constraint inputted to the layout tool is corrected; but if timing analysis is performed for another timing constraint, a new setup error may occur for the signal path. Once a setup error occurs, correction of the setup error is difficult, nor is it an easy matter to decide where a delay buffer should be inserted.
FIG. 2 explains the above problem. FIG. 2A is a circuit example, having four flip-flops FF1 to FF4 and an AND gate AND. In FIG. 2B, the timing chart is shown. Along the signal path from the flip-flop FF3 to the AND gate and then to the flip-flop FF2, the output data Q3 is outputted in response to the rising edge of the clock CK3, and supplied as the input data D2 to the flip-flop FF2. Along the signal path from the flip-flop FF1 to the flip-flop FF2, the output data Q1 is outputted in response to the rising edge of the clock CK1 and supplied as the input data D2 to the flip-flop FF2. If the change in the Q3-D2 signal and the change in the Q1-D2 signal are assumed to be as shown, then the setup time ST and hold time HT for the flip-flop FF2 with respect to the clock CK2 are as shown.
In the layout process, layout is performed so as to satisfy the setup time ST requirement; suppose that, as a result, the hold time HT is too short and a hold error occurs. In this case, suppose that a delay buffer is inserted between the AND gate and the flip-flop FF2, delaying the Q1-D2 signal, lengthening the hold time HT and correcting the hold error. As a result, signals on a signal path which share the signal path into which the delay buffer was inserted are also delayed, so that for example in the case of the Q3-D2 signal, the setup time ST is shortened, possibly causing a setup error. If a delay buffer is inserted between the flip-flop FF1 and the AND gate, the Q1-D4 signal is also affected, and in similar fashion a setup error may occur.
As a second problem, in the case of a plurality of timing constraints corresponding to a plurality of operating modes, the hold times and setup times will be different, and correction of hold errors so as to satisfy all these conditions becomes extremely complicated. As a result, automatic correction of hold errors by computer is no longer possible, and ordinarily manual correction is performed by a skilled designer.
In this way, when correcting timing errors, if layout is performed with priority given to the setup time and hold errors are then corrected, there is no method for inserting delay buffers without causing new setup errors, nor is there a method for inserting delay buffers to correct a hold error for a given timing constraint while preventing the occurrence of new setup errors under different timing constraints, and so the automatic correction of hold errors by a computer has been impossible.